As is well known to those skilled in the digital electronics arts, a microprocessor-based electronic system or assembly includes a microprocessor which functions as a central processing unit (CPU). The CPU is interconnected with other system components including random access and read only memory circuits (RAM's and ROM's) through various digital signal lines, frequently structured as system data and address buses, which carry streams of digitally-encoded data. Each such assembly includes one or more input/output (I/O) circuits which permit data to be coupled into and out of the microprocessor based system from a wide variety of input and output devices such as manually-operated keyboards and switches, information display devices, analog-to-digital converters, digital-to-analog converters, and various types of transducers and interfaces that provide signals representative of desired system stimuli and/or respond to an alarm or control signal provided by the microprocessor-based electronic system. As is also known to those skilled in the art, a microprocessor-based system or assembly often includes other types of digital circuit arrangements, such as buffer stages, decoding networks and variously-configured arrangements of logic gates.
Since microprocessor-based systems have fewer components than comparable circuits employing discrete logic elements arranged to exhibit the same or similar operational capabilities as the microprocessor based systems, and since microprocessor-based systems can be manufactured at relatively low cost, the use of such systems has grown dramatically. This growth continues as new microprocessor-based products are developed and as new microprocessor circuits and associated memory devices of increased signal-processing capability become available. In this regard, the use of microprocessor-based systems has not been limited to replacements for electronic systems and assemblies that were previously realized by relatively complex arrangements of discrete logic circuitry but has resulted in a wide variety of new products including small computers for business and home use and electronic games. Moreover, since microprocessor-based arrangements are reliable and can be manufactured at a relatively low cost, such circuits and system are rapidly replacing electro-mechanical arrangements such as, for example, the control and timer assemblies used in home appliances, the electromechanical arrangements of pinball and various gaming machines, and the electromechanical computing and tabulation assemblies utilized within cash registers, typewriters and other business machines.
Although microprocessor-based systems and assemblies have numerous advantages from the standpoint of both the manufacturer and the system user, such systems exhibit certain disadvantages and drawbacks relative to the testing and troubleshooting that are necessary to maintain satisfactory quality control during the manufacturing process and to maintain and repair such a system once it has been placed in service. In this regard, since the system primarily consists of integrated circuits that are interconnected with one another by means of digital signal lines often configured in a system bus architecture, relatively few test points are available. Moreover, very few system failures can be detected by testing relatively static signal conditions within the system. Satisfactory testing and troubleshooting require the detection of system control, status, addressing and data signals which appear on the digital signal lines, and on the digital signal lines of the system bus as a rapidly changing series or string of digitally-encoded data words. Since the digital signal lines of the system bus are typically bidirectional, with data signals being coupled to and from various system components, use of traditional testing concepts, which involve stimulating a device in a controlled manner and monitoring the response thereto, becomes a relatively complex task.
Accordingly, apparatus which permits an operator to access and examine various signals in a microprocessor-based assembly or system has not satisfied the need for test equipment which can be used in a wide variety of situations ranging from manufacturing tests of electronic assemblies and subassemblies to field service and repair of completed units. For example, to facilitate the design of microprocessor-based electronic assemblies and systems, microprocessor manufacturers and others have developed relatively complex apparatus generally known as microprocessor development systems which permit an operator to interact with a microprocessor system by, for example, selectively establishing address and control signals as well as the value of ROM-stored signals as he or she sequentially steps through the microprocessor logic sequence or program. Moreover, most microprocessor development systems allow the operator to store a sequence of digitally-encoded signals that appear on the digital signal lines of the system bus between any two specific system states such as selected address signals, specified system command signals or specified states of the system data bus. The stored information can then be examined to locate programming faults.
Although microprocessor development systems provide substantial assistance in designing microprocessor-based systems by allowing the system designer to establish, evaluate and debug the system programming, such apparatus is of little use in manufacturing and field service environments since hardware-related faults and failures are not located. Moreover, satisfactory operation of such equipment requires an in-depth understanding of the manner in which the microprocessor-based system or the unit under test (UUT) is programmed and sequenced and requires substantial training and experience in the design and analysis of programmed apparatus.
To extend the capabilities of microprocessor development systems so as to permit detection and isolation of hardware-related faults and failures, such systems have been combined with "in-circuit emulation" techniques wherein the test arrangement is configured to replace the microprocessor circuit of the assembly being tested, i.e., the UUT. Interconnected in this manner, the test arrangement operates in conjunction with the UUT to execute diagnostic routines or programs that are organized to detect faults and, in many cases, to isolate the fault to a particular component or group of components. The instructions and data utilized in these diagnostic tests are generally stored in the memory of the microprocessor development system, and are coupled to the digital signal lines of the microprocessor bus during the in-circuit emulation routine. Examples of such in circuit testers are contained in Bhaskar et al., U.S. Pat. No. 4,455,654 and Scott et al., U.S. Pat. No. 4,709,366, both commonly assigned with the instant application.
To facilitate use with various types of microprocessor circuits, the microprocessor development system is configured so that the microprocessor circuit and associated memory devices, interface circuits and other digital logic circuits which must be configured for testing a specific UUT are provided in an interface pod. With this configuration, the interface pod is interchangeable and a system or assembly that employs a particular type of microprocessor is tested by connecting an appropriately configured interface pod to a general purpose circuit tester or development system. The interface pod is then connected to the UUT by means of an interface pod cable assembly including a connector which mates with the microprocessor socket of the UUT.
In operation, the interface pod is controlled by a circuit tester to simulate the signals normally generated by the microprocessor and to exercise and control other components of the UUT connected to the various signal lines including those comprising any system buses. The interface pod also detects signals on various digital signal lines of the bus to be received by the microprocessor. The detected signals are checked by the circuit tester for proper signal level, timing, etc.
If the interconnections between the interface pod and the other components connected to the digital signal lines of the UUT are faulty or inoperative because of a signal line fault, the interface pod may not be able to exercise the components over the signal line or may receive erroneous signals from the components because of the signal line fault rather than due to a component or software fault. To account for the possibility of a signal line fault prior to initiating system logic testing, as a first step in the testing process the circuit tester exercises or "wiggles" the signal lines, including those comprising any system data and address buses, which are normally controlled by the microprocessor. Each signal line is driven with predetermined logic level signals and the resultant voltage level on the signal line is monitored to determine if all signal lines are being properly driven. If the circuit tester detects an abnormal logic level, this indicates a short-circuit or open-circuit condition on the respective signal line(s). If the interface pod is not able to drive the appropriate signal lines to the desired logic level, it is not possible to control and test the other components over that signal line. During subsequent steps of the testing process the circuit tester continues to monitor signal line loading to detect drive faults not identified during the initial testing step.
In digital signal line testers of the prior art, a resistor is placed between each of the interface pod output drivers and the corresponding interface pod output terminal connected to the UUT which are in turn connected to the digital signal lines of the UUT. The voltage across the resistor is monitored to detect whether the logic level on the interface pod output terminal matches the logic level on the driver side of the resistor. If the voltage drop detected across the series resistor exceeds a predetermined value, a drive fault is deemed to exist.
Drive faults can be caused by various circuit abnormalities including a short-circuit or faulty component driving the signal line, e.g., short-circuit to ground, to a high logic level source, or to other signal lines. A drive fault can also be caused by two logic devices simultaneously driving a signal line, for example the tester and a device on the UUT, resulting in a collision. In this situation, driver fighting driver, the series resistor method will not always detect the fault. This is because the voltage drop across the series resistor depends on which driver is "stronger", i.e., supplies the greater current to the signal line.
Use of a series resistor to detect signal line driving faults also limits the maximum speed of the tester. This is because the series resistor together with capacitive loads of and on the signal line form an RC circuit, degrading the rise and fall time characteristics of the test signals and limiting the usable digital test signal frequency. The resultant RC circuit further has the disadvantage of increasing the propagation delay time between the interface pod and the UUT. To mitigate this problem, series resistance values are kept to a minimum, resulting in reduced voltage drops across the series resistors. The reduced voltage requires additional amplification to detect a drive fault while resulting in some errors going undetected because of reduced sensitivity.
A need therefore exists for a digital signal line fault detecting buffer capable of supplying a test signal to a UUT without degrading the test signal rise and fall time characteristics.
A need further exists for a digital signal line fault detecting buffer capable of operating at high digital frequencies.
A need still further exists for a digital signal line fault detecting buffer which introduces a minimum propagation delay between a circuit tester and a signal line of a UUT.
A need further exists for a digital signal line fault buffer for a circuit tester which precisely senses the amount of current required to drive a UUT.
A need still further exists for a digital signal line fault detecting buffer which reduces the amount of resistance placed in line with the bus.
Accordingly, an object of the invention is to provide a current sensing buffer for digital signal lines including bus testing applications capable of supplying test signals to a UUT without degrading test signal rise and fall time characteristics.
A further object of the invention is to provide a digital signal line buffer capable of supplying high frequency digital test signals to a UUT.
Another object of the invention is to provide a current sensing buffer which minimizes test signal propagation delays.
Still another object of the invention is to provide a current sensing buffer with enhanced drive fault detection capabilities.
Still a further object of the invention is to provide a digital signal line tester output buffer having a low output impedance.